System Diagrams

Two high-level views of how ESP-GUARDX is put together. The first shows the major functional modules and how field signals, operator interaction, and external systems connect to the device. The second walks through the signal acquisition path from the field to live display and event recording.

System Block Diagram

flowchart LR
    subgraph Inputs["Field Inputs"]
        direction TB
        V[Voltage Transformers<br/>3-phase]
        C[Current Transformers /<br/>Rogowski Coils]
        S[Downhole & Wellhead<br/>Sensors]
        P[PLC / External<br/>Modbus Devices]
    end

    subgraph Dev["ESP-GUARDX Device"]
        direction TB
        A[High-speed ADC]
        CPU[Processing &<br/>Analytics Engine]
        HMI[Touchscreen HMI]
        ST[Internal Storage]
    end

    subgraph Out["Connectivity & Output"]
        direction TB
        R[RS-485<br/>Modbus RTU]
        U[USB / SD Card<br/>Export]
    end

    V --> A
    C --> A
    A --> CPU
    S --> CPU
    P <--> CPU
    CPU --> HMI
    HMI --> CPU
    CPU --> ST
    CPU --> R
    ST --> U

• Voltage and current signals from the switchgear pass through transformers into the high-speed ADC for digitization.
• Downhole, wellhead, and flow sensors connect to the processor via serial lines.
• External PLCs and Modbus devices exchange data with the processor for integrated monitoring and control.
• The processing engine runs signal analysis, event detection, and optimization, feeding results to the touchscreen and to internal storage.
• Connectivity is provided via RS-485 (Modbus RTU) for industrial integration, and USB / SD card for data export.

Signal Acquisition Flow

flowchart LR
    subgraph Field["Field / Switchgear"]
        direction TB
        MV[Motor Voltage<br/>3-phase]
        MC[Motor Current<br/>3-phase]
    end

    VTs[Voltage Transformers<br/>step-down]
    CTs[Current Transformers /<br/>Rogowski Coils]

    subgraph Front["Front-End"]
        direction TB
        Cond[Signal Conditioning]
        ADC[High-speed ADC]
    end

    subgraph Proc["Processing"]
        direction TB
        DSP[RMS, Phasors,<br/>Power Calculations]
        Harm[Harmonic<br/>Decomposition]
        Evt[Threshold &<br/>Event Engine]
    end

    MV --> VTs --> Cond
    MC --> CTs --> Cond
    Cond --> ADC
    ADC --> DSP
    DSP --> Harm
    DSP --> Evt
    Harm --> Evt
    DSP --> Live[Live Display<br/>& Oscilloscope]
    Evt --> Rec[Event Recording<br/>Pre- & Post-trigger]

Voltage and current from the switchgear are reduced by transformers, conditioned, and digitized at high speed. The processor then runs RMS, phasor, and power calculations in parallel with harmonic decomposition, and continuously compares results against configured thresholds to detect events.